Market situation & the need for design constraint technology:
Silicon design is becoming vastly more complicated and costly, and harder to design and verify. Today’s SoCs drive this exploding complexity – thanks to raw design size, increasing use of IP blocks, advanced technology node, number of clocks and clocked domains, and complexity of constraints to close timing across all combinations of corners and modes. There is a demand for a comprehensive product to generate and validate design constraints that correlate with static timing analysis engines to ensure design correctness.
The huge cost of an error in constraints, clocking or timing often forces design teams to adopt a minimization strategy – designing a completely minimal, safe set of timing constraints that are the least prone to error. Experienced leaders in the silicon design field recognize this as a complex, multi-faceted problem that requires a variety of capabilities and techniques to attack. Simple structural or semantic tools and approaches will only catch simple problems while emitting copious numbers of false-positive errors requiring designer review. The solution should aid in the goal of helping the design team create design constraints that cover the requirements of the design, allowing it to meet its power, performance and area goals while minimizing the risk of a respin due to a clocking or timing issue.
Timevision™ is a comprehensive platform solution to generate and validate timing constraints that correlate with static timing analysis engines to ensure design correctness. Using multi-core software architecture, patented analysis algorithms, and innovative formal verification technology, the founders of Ausdia created Timevision to handle large, complex SoC designs–especially above 100+ million instances. Timevision handled a design with more than Billion instances.
A solution for constraints development and verification, allowing system-on-chip (SoC) and integrated circuit (IC) developers to make massive productivity gains across the design flow.
A clean, consistent and correct set of timing constraints (SDC) is a necessity to get the best PPA (power, performance and area) from timing-driven implementation tools. Timevision Check SDC provides over 200 checks on the SDC, aids in the design of new SDC constraints, and works on RTL and gate-level designs from early RTL to signoff gate netlist.
SoCs have incorporated hierarchical design techniques for some time – using multiple, smaller blocks to close timing, with a “top-level” that incorporates all the blocks and is the ultimate design that is taped out. However, the creation and verification of timing constraints across the disparate hierarchies becomes paramount in such flows, since inconsistent SDCs will cause the resulting blocks to not line up with the tape out requirements of the top-level design.
Timevision SoC Hierarchy performs SDC consistency checking between top-level and an arbitrary number of blocks – including thorny issues such as boundary constraint checking – as well as performing constraint integration (bottom up design) and constraint demotion (top-down design).
Constraints on functionality, power and reuse often compel designers to make their RTL have multiple operating modes, controllable by constant settings in firmware or clock controllers. Back-end engineers need to design timing constraints that cover all possible operating modes of the RTL.
This is a technically challenging task, not including the need to verify the resulting SDC. Timevision Mode-Merge takes an arbitrary number of SDC files, representing multiple operating modes, and produces a single SDC file that covers all modes in the one run – reducing the number of back-end licenses needed to close the block, while ensuring all timing paths are covered in the single merged mode.
With designs having upwards of 1,000 clocks to verify as part of a design signoff flow, CDC is a critical check in today’s complex SoC designs. Timevision CDC directly utilizes SDC timing constraints to verify clock domain crossings with a robust suite of checks, including synchronization and handshakes, FIFOs, resets and synchronized structure checks. Working with either RTL or gate-level netlists at up to 1 billion instances, Timevision CDC can be used all the way to gate-level signoff for CDC checking.
Timevision SOC Budgeter handles the SDC integration and management tasks of hierarchical SoC design. However, the generation of timing budgets (allocation of allowable time between the SoC partitions) becomes paramount also. Timevision SOC Budgeter uses SDFs, timing reports and physical data (LEF/DEF) to produce and manage accurate timing budgets for the blocks used in hierarchical implementation flows.
Timing Exceptions (multi-cycle paths and false paths) are used extensively to relax timing in critical or known areas of a design. However, these exceptions must be verified in order to provide confidence the design will work once fabricated.
Timevision Formal SDC uses static formal verification techniques to formally check timing exceptions, and provides a full suite of features to generate SVA (System Verilog Assertions) to check and debug timing exceptions in functional simulation engines.
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